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this is information on a product in full production. march 2012 doc id 022567 rev 1 1/28 1 m93s66-125 M93S56-125 m93s46-125 automotive 4-kbit, 2-kbit and 1-kbit microwire serial eeprom with block protection datasheet ? production data features industry standard microwire tm bus single supply voltage: 2.5 to 5.5 v single organization: by word (x16) programming instructions that work on: word or entire memory self-timed programming cycle with auto-erase user-defined write-protected area page write mode (4 words) ready/busy signal during programming speed: 2-mhz clock rate, 5 ms write time sequential read operation enhanced esd/latch-up behavior more than 1 million erase/write cycles more than 40-year data retention so8 (mn) 150 mil width www.st.com
contents m93s66-125 M93S56-125 m93s46-125 2/28 doc id 022567 rev 1 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 power-on data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 write enable and write disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4 page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 write all . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 write protection and the protec tion register . . . . . . . . . . . . . . . . . . . . 16 4.1 protection register read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 protection register enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 protection register clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.4 protection register write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.5 protection register disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 common i/o operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 clock pulse counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
m93s66-125 M93S56-125 m93s46-125 list of tables doc id 022567 rev 1 3/28 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 2. instruction set for the m93s46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. instruction set for the m93s56, m93s66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5. operating conditions (m93sx6-w, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 6. ac measurement conditions (m93sx6-w, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . 20 table 7. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8. dc characteristics (m93sx6-w, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 9. ac characteristics (m93sx6-w, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 10. so8 narrow ? 8 lead plastic small outline, 150 mils body width, mechanical data . . . . . . . 25 table 11. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 12. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
list of figures m93s66-125 M93S56-125 m93s46-125 4/28 doc id 022567 rev 1 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. 8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. read, write, wen and wds sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. pawrite and wral sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. pread, prwrite and pren sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 6. prclear and prds sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7. write sequence with one clock glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 8. ac testing input output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 9. synchronous timing (start and opcode input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 10. synchronous timing (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 11. synchronous timing (write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 12. so8 narrow ? 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . 25
m93s66-125 M93S56-125 m93s46-125 description doc id 022567 rev 1 5/28 1 description the m93s66-125, M93S56-125 and m93s46-125 are a range of 4-kbit, 2-kbit, and 1-kbit serial electrically erasable programmab le memory (eeprom) products. they are collectively referred to as m93sx6-125. figure 1. logic diagram the m93sx6-125 is accessed through a serial data input (d) and serial data output (q) using the microwire bus protocol. the memory is divided into 256, 128 and 64 x16-bit words (respectively for m93s66-125, M93S56-125 and m93s46-125). the m93sx6-125 is accessed by a set of instructions which includes read, write, page write, write all and instructions used to set the memory protection. these are summarized in ta b l e 2 and ta bl e 3 . a read data from memory (read) instruction loads the address of the first word to be read into an internal address pointer. the data contained at this address is then clocked out serially. the address pointer is automatically incremented after the data is output and, if the table 1. signal names signal name description s chip select input d serial data input q serial data output c serial clock pre protection register enable w write enable v cc supply voltage v ss ground
description m93s66-125 M93S56-125 m93s46-125 6/28 doc id 022567 rev 1 chip select input (s ) is held high, the m93sx6-125 can output a sequential stream of data words. in this way, the memory can be read as a data stream from 16 to 4096 bits (for the m93s66-125), or continuously as the address counter automatically rolls over to 00h when the highest address is reached. within the time required by a programming cycle (t w ), up to 4 words may be written with help of the page write instruction. the whole memory may also be erased, or set to a predetermined pattern, by using the write all instruction. within the memory, a user defined area may be protected against further write instructions. the size of this area is defined by the content of a protection register, located outside of the memory array. as a final protection step, data may be permanently protected by programming a one time programming (otp) bit which locks the protection register content. programming is internally self-timed (the ex ternal clock signal on serial clock (c) may be stopped or left running after the start of a write cycle) and does not require an erase cycle prior to the write instruction. the write instruction writes 16 bits at a time into one of the word locations of the m93sx6-125, the page write instruction writes up to 4 words of 16 bits to sequential locations, assuming in both cases that all addresses are outside the write protected area. after the start of the programmi ng cycle, a busy/ready signal is available on serial data output (q) wh en chip select input (s ) is driven high. an internal power-on data protection mechanism in the m93sx6-125 inhibits the device when the supply is too low. figure 2. 8-pin package connections (top view) note: see section 9: package mechanical data section for package dimensions, and how to identify pin-1.
m93s66-125 M93S56-125 m93s46-125 power-on data protection doc id 022567 rev 1 7/28 2 power-on data protection to prevent data corruption and inadvertent write operations during power-up, a power-on reset (por) circuit resets all internal programming circuitry, and sets the device in the write disable mode. at power-up and power-down, the device must not be selected (that is, chip select input (s ) must be driven low) until the supply voltage reaches the operating value v cc specified in section 8: dc and ac parameters . when v cc reaches its valid level, the device is properly reset (in the write disable mode) and is ready to decode and execute incoming instructions. for the m93sx6-125, the por threshold voltage is around 1.5 v. 3 instructions the instruction set of the m93s x6-125 devices contains seven instructions, as summarized in table 2 and table 3 . each instruction consists of the following: each instruction is preceded by a rising edge on chip select input (s ) with serial clock (c) being held low. a start bit, which is the first ?1? read on serial data input (d) during the rising edge of serial clock (c). two opcode bits, read on serial data input (d) during the rising edge of serial clock (c). (some instructions also use the first two bits of the address to define the opcode). the address bits of the byte or word that is to be accessed. for the m93s46-125, the address is made up of 6 bits (see ta b l e 2 ). for the M93S56-125 and m93s66-125, the address is made up of 8 bits (see ta b l e 3 ). the m93sx6-125 devices are fabricated in cmos technology and are therefore able to run as slow as 0 hz (static input signals) or as fast as the maximum ratings specified in ta bl e 9 .
instructions m93s66-125 M93S56-125 m93s46-125 8/28 doc id 022567 rev 1 table 2. instruction set for the m93s46 instruction description w pre start bit opcode address (1) data required clock cycles additional comments read read data from memory x 0 1 10 a5-a0 q15-q0 write write data to memory 1 0 1 01 a5-a0 d15-d0 25 write is executed if the address is not inside the protected area paw r i t e page write to memory 10 1 11 a5-a0 n x d15-d0 9 + n x 16 write is executed if all the n addresses are not inside the protected area wral write all memory with same data 1 0 1 00 01 xxxx d15-d0 25 write all data if the protection register is cleared wen write enable 1 0 1 00 11 xxxx 9 wds write disable x 0 1 00 00 xxxx 9 prread protection register read x 1 1 10 xxxxxx q5-q0 + flag data output = protection register content + protection flag bit prwrite protection register write 11 1 01 a5-a0 9 data above specified address a5-a0 are protected prclear protection register clear 1 1 1 11 111111 9 protect flag is also cleared (cleared flag = 1) pren protection register enable 1 1 1 00 11xxxx 9 prds protection register disable 1 1 1 00 000000 9 otp bit is set permanently 1. x = don't care bit.
m93s66-125 M93S56-125 m93s46-125 instructions doc id 022567 rev 1 9/28 table 3. instruction set for the m93s56, m93s66 instruction description w pre start bit opcode address (1), (2) data required clock cycles additional comments read read data from memory x 0 1 10 a7-a0 q15-q0 write write data to memory 1 0 1 01 a7-a0 d15-d0 27 write is executed if the address is not inside the protected area paw r i t e page write to memory 10 1 11 a7-a0 n x d15-d0 11 + n x 16 write is executed if all the n addresses are not inside the protected area wral write all memory with same data 1 0 1 00 01xxxxxx d15-d0 27 write all data if the protection register is cleared wen write enable 1 0 1 00 11xxxxxx 11 wds write disable x 0 1 00 00xxxxxx 11 prread protection register read x1 1 10 xxxxxxx x q7-q0 + flag data output = protection register content + protection flag bit prwrite protection register write 11 1 01 a7-a0 11 data above specified address a7-a0 are protected prclear protection register clear 1 1 1 11 11111111 11 protect flag is also cleared (cleared flag = 1) pren protection register enable 1 1 1 00 11xxxxxx 11 prds protection register disable 1 1 1 00 00000000 11 otp bit is set permanently 1. x = don't care bit. 2. address bit a7 is not decoded by the M93S56-125.
instructions m93s66-125 M93S56-125 m93s46-125 10/28 doc id 022567 rev 1 figure 3. read, write, wen and wds sequences 1. for the meanings of an, xn, qn and dn, see table 2 and table 3 . ai00889d 1 1 0 an a0 qn q0 data out d s q s write addr op code 1 0an a0 data in d q op code dn d0 1 busy ready s write enable 1 0xnx0 d op code 1 01 s write disable 1 0xnx0 d op code 0 0 0 check status addr pre read pre w pre w pre
m93s66-125 M93S56-125 m93s46-125 instructions doc id 022567 rev 1 11/28 3.1 read the read data from memory (read) instruction outputs serial data on serial data output (q). when the instruction is received, the opcode and address are decoded, and the data from the memory is transferred to an output shift register. a dummy 0 bit is output first, followed by the 16-bit word, with the most significant bit first. output data changes are triggered by the rising edge of serial clock (c). the m93sx6-125 automatically increments the internal address register and clocks out the next byte (or word) as long as the chip select input (s ) is held high. in this case, the dummy 0 bit is not output between bytes (or words) and a continuous stream of data can be read. 3.2 write enable and write disable the write enable (wen) instruction enables the future execution of write instructions, and the write disable (wds) instruction disables it. when power is first applied, the m93sx6-125 initializes itself so that write instructions are disabled. after a write enable (wen) instruction has been executed, writing remains enabled until a write disable (wds) instruction is executed, or until v cc falls below the power-on reset threshold voltage. to protect the memory contents from accidental corruption, it is advisable to issue the write disable (wds) instruction after every write cycle. the read data from memory (read) instruction is not affected by the write enab le (wen) or write disable (wds) instructions. 3.3 write the write data to memory (write) instruction is composed of the start bit plus the opcode followed by the address and the 16 data bits to be written. write enable (w ) must be held high before and during the instruction. input address and data, on serial data input (d) are sampled on the rising edge of serial clock (c). after the last data bit has been sampled, the chip select input (s ) must be taken low before the next rising edge of serial clock (c). if chip select input (s ) is brought low before or after this specific time fram e, the self-timed programming cy cle will not be started, and the addressed location will not be programmed. while the m93sx6-125 is performing a write cycle, but after a delay (t slsh ) before the status information becomes availabl e, chip select input (s ) can be driven high to monitor the status of the write cycle: serial data output (q) is driven low while the m93sx6-125 is still busy, and high when the cycle is complete, and the m93sx6-125 is ready to receive a new instruction. the m93sx6-125 ignores any data on the bus while it is busy on a write cycle. once the m93sx6-125 is ready, serial data output (q) is driven high, and remains in this state until a new start bit is decoded or the chip select input (s ) is brought low. programming is internally self-t imed, so the external serial clock (c) may be disconnected or left running after the start of a write cycle.
instructions m93s66-125 M93S56-125 m93s46-125 12/28 doc id 022567 rev 1 figure 4. pawrite and wral sequence 1. for the meanings of an, xn and dn, please see table 2 and table 3 . 3.4 page write a page write to memory (pawrite) instruction contains the first address to be written, followed by up to 4 data words. after the receipt of each data word, bits a1-a0 of the internal address register are incremented, the high order bits remaining unchanged (a7-a2 for m93s66-125, m93s56- 125; a5-a2 for m93s46-125). users must take care, in the software, to ensure that the last word address has the same upper order address bits as the initial address transmitted to avoid address roll-over. the page write to memory (pawrite) instruct ion will not be executed if any of the 4 words addresses the protected area. write enable (w ) must be held high before and during the instruction. input address and data, on serial data input (d) are sampled on the rising edge of serial clock (c). after the last data bit has been sampled, the chip select input (s ) must be taken low before the next rising edge of serial clock (c). if chip select input (s ) is brought low before or ai00890c s page write 1 1an a0 data in d q op code dn d0 1 busy ready check status addr pre w s write all 1 0xnx0 data in d q op code dn d0 0 busy ready check status addr pre w 01
m93s66-125 M93S56-125 m93s46-125 instructions doc id 022567 rev 1 13/28 after this specific time fram e, the self-timed programming cy cle will not be started, and the addressed location will not be programmed. while the m93sx6-125 is performing a write cycle, but after a delay (t slsh ) before the status information becomes availabl e, chip select input (s ) can be driven high to monitor the status of the write cycle: serial data output (q) is driven low while the m93sx6-125 is still busy, and high when the cycle is complete, and the m93sx6-125 is ready to receive a new instruction. the m93sx6-125 ignores any data on the bus while it is busy on a write cycle. once the m93sx6-125 is ready, serial data output (q) is driven high, and remains in this state until a new start bit is decoded or the chip select input (s ) is brought low. programming is internally self-t imed, so the external serial clock (c) may be disconnected or left running after the start of a write cycle. 3.5 write all the write all memory with same data (wral) in struction is valid only after the protection register has been cleared by executing a protection register clear (prclear) instruction. the write all memory with same data (wral) instruction simultaneously writes the whole memory with the same data word given in the instruction. write enable (w ) must be held high before and during the instruction. input address and data, on serial data input (d) are sampled on the rising edge of serial clock (c). after the last data bit has been sampled, the chip select input (s ) must be taken low before the next rising edge of serial clock (c). if chip select input (s ) is brought low before or after this specific time fram e, the self-timed programming cy cle will not be started, and the addressed location will not be programmed. while the m93sx6-125 is performing a write cycle, but after a delay (t slsh ) before the status information becomes availabl e, chip select input (s ) can be driven high to monitor the status of the write cycle: serial data output (q) is driven low while the m93sx6-125 is still busy, and high when the cycle is complete, and the m93sx6-125 is ready to receive a new instruction. the m93sx6-125 ignores any data on the bus while it is busy on a write cycle. once the m93sx6-125 is ready, serial data output (q) is driven high, and remains in this state until a new start bit is decoded or the chip select input (s ) is brought low. programming is internally self-t imed, so the external serial clock (c) may be disconnected or left running after th e start of a write cycle.
instructions m93s66-125 M93S56-125 m93s46-125 14/28 doc id 022567 rev 1 figure 5. pread, prwrite and pren sequences 1. for the meanings of an, xn and dn, please see table 2 and table 3 . ai00891d 1 1 0 xn x0 data out d s q s protect register write addr op code 1 0an a0 d q op code 1 busy ready s protect register enable 1 0xnx0 d op code 1 01 check status addr pre protect register read pre w pre w an a0 f f = protect flag
m93s66-125 M93S56-125 m93s46-125 instructions doc id 022567 rev 1 15/28 figure 6. prclear and prds sequences 1. for the meanings of an, xn and dn, please see table 2 and table 3 . ai00892c s protect register clear 1 1 d q op code 1 busy ready check status addr pre w 111 s protect register disable 1 0 d q op code 0 busy ready check status addr pre w 000
write protection and the protection register m93s66-125 M93S56-125 m93s46-125 16/28 doc id 022567 rev 1 4 write protection and the protection register the protection register on the m93sx6-125 is used to adjust the amount of memory that is to be write protected. the write protected area extends from the address given in the protection register, up to the top address in the m93sx6-125 device. two flag bits are used to indicate the protection register status: protection flag: this is used to enable/disable protection of the write-protected area of the m93sx6-125 memory otp bit: when set, this disables access to the protection register, and thus prevents any further modifications to the value in the protection register. the lower-bound memory address is written to the protection register using the protection register write (prwrite) instruction. it can be read using the protection register read (prread) instruction. the protection register enable (pren) instruction must be executed before any prclear, prwrite or prds instruction, and with appropriate levels applied to the protection enable (pre) and write enable (w ) signals. write-access to the protection register is achieved by executing the following sequence: execute the write enable (wen) instruction execute the protection register enable (pren) instruction execute one prwrite, prclear or prds instructions, to set a new boundary address in the protection register, to clear the protection address (to all 1s), or permanently to freeze the value held in the protection register. 4.1 protection register read the protection register read (prread) instruction outputs, on serial data output (q), the content of the protection register, followed by the protection flag bit. the protection enable (pre) signal must be driven high before and during the instruction. as with the read data from memory (read) instruction, a dummy 0 bit is output first. since it is not possible to distinguish between the protection register being cleared (all 1s) or having been written with all 1s, the user must ch eck the protection flag status (and not the protection register content) to ascertain the setting of the memory protection. 4.2 protection register enable the protection register enable (pren) instruction is used to authorize the use of instructions that modify the protection register (prwrite, prclear, prds). the protection register enable (pren) instruction doe s not modify the protection flag bit value. note: a write enable (wen) instruction must be executed before the protection register enable (pren) instruction. both the protection enable (pre) and write enable (w ) signals must be driven high during the instruction execution.
m93s66-125 M93S56-125 m93s46-125 write protection and the protection register doc id 022567 rev 1 17/28 4.3 protection register clear the protection register clear (prclear) instruction clears the address stored in the protection register to all 1s, so that none of the memory is write-protected by the protection register. however, it should be noted that all the memory remains protected, in the normal way, using the write enable (wen) and write disable (wds) instructions. the protection register clear (prclear) instruction clears the protection flag to 1. both the protection enable (pre) and write enable (w ) signals must be driven high during the instruction execution. note: a protection register enable (pren) instruction must immediately precede the protection register clear (prclear) instruction. 4.4 protection register write the protection register write (prwrite) instruction is used to write an address into the protection register. this is the address of the fi rst word to be protected. after the protection register write (prwrite) instruction has been executed, all memory locations equal to and above the specified address are protected from writing. the protection flag bit is set to 0, and can be read with protection register read (prread) instruction. both the protection enable (pre) and write enable (w ) signals must be driven high during the instruction execution. note: a protection register enable (pren) instruction must immediately precede the protection register write (prwrite) instruction, but it is not necessary to execute first a protection register clear (prclear). 4.5 protection register disable the protection register disable (prds) instruction sets the one time programmable (otp) bit. this instruction is a one time on ly instruction which latches the protection register content, this content is therefore unalterable in the future. both the protection enable (pre) and write enable (w ) signals must be driven high during the instruction execution. the otp bit cannot be directly read, it can be checked by reading the content of the protection register, using the protection register read (prread) instruction, then by writing this same value back into the prot ection register, using the protection register write (prwrite) instruction. when the otp bit is set, the ready/busy status cannot appear on serial data output (q). when the otp bit is not set, the busy status appears on serial data output (q). note: a protection register enable (pren) instruction must immediately precede the protection register disable (prds) instruction.
common i/o operation m93s66-125 M93S56-125 m93s46-125 18/28 doc id 022567 rev 1 5 common i/o operation serial data output (q) and serial data input (d) can be connected together, through a current limiting resistor, to form a common, single-wire data bus. some precautions must be taken when operating the memory in this way, mostly to prevent a short circuit current from flowing when the last address bit (a0) clashes with the first data bit on serial data output (q). please see an394 (microwire eeprom common i/o operation application note) for details. figure 7. write sequence with one clock glitch 6 clock pulse counter in a noisy environment, the number of pulses received on serial clock (c) may be greater than the number delivered by the bus master (the microcontroller). this can lead to a misalignment of the instruction of one or more bits (as shown in figure 7 ) and may lead to the writing of erroneous data at an erroneous address. to combat this problem, the m93sx6-125 has an on-chip counter that counts the clock pulses from the start bit until the fa lling edge of the chip select input (s ). if the number of clock pulses received is not the number expected, the write, pawrite, wrall, prwrite or prclear instruction is aborted, and the contents of the memory are not modified. the number of clock cycles expected for each instruction, and for each member of the m93sx6-125 family, are summarized in ta b l e 2 to ta bl e 3 . for example, a write data to memory (write) instruction on the m93s56 (or m93s66) expects 27 clock cycles from the start bit to the falling edge of chip select input (s ). for example: 1 start bit + 2 op-code bits + 8 address bits + 16 data bits ai01395 s an-1 c d write start d0 "1" "0" an glitch an-2 address and data are shifted by one bit
m93s66-125 M93S56-125 m93s46-125 maximum rating doc id 022567 rev 1 19/28 7 maximum rating stressing the device above the rating listed in ta b l e 4 may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operat ing sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 4. absolute maximum ratings symbol parameter min. max. unit t stg storage temperature ?65 150 c t lead lead temperature during soldering see note (1) 1. compliant with jedec std j-st d-020b (for small body, sn-pb or pb assembly), the st ecopack ? 7191395 specification, and the european directive on re strictions on hazardous substances (rohs) 2002/95/eu c v out output range (q = v oh or hi-z) ?0.50 v cc +0.5 v v in input range ?0.50 v cc +1 v v cc supply voltage ?0.50 6.5 v v esd electrostatic discharge voltage (human body model) (2) 2. jedec std jesd22-a114a (c1=100 pf, r1=1500 , r2=500 ) ?4000 4000 v
dc and ac parameters m93s66-125 M93S56-125 m93s46-125 20/28 doc id 022567 rev 1 8 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. note: output hi-z is defined as the point where data out is no longer driven. note: output hi-z is defined as the point where data out is no longer driven. figure 8. ac testing input output waveforms table 5. operating conditions (m93sx6-w, device grade 3) symbol parameter min. max. unit v cc supply voltage 2.5 5.5 v t a ambient operating temperature ?40 125 c table 6. ac measurement conditions (m93sx6-w, device grade 3) symbol parameter min. max. unit c l load capacitance 100 pf input rise and fall times 50 ns input pulse voltages 0.2 v cc to 0.8 v cc v input timing reference voltages 0.3v cc to 0.7v cc v output timing reference voltages 0.3v cc to 0.7v cc v table 7. capacitance (1) 1. sampled only, not 100% tested, at t a =25c and a frequency of 1 mhz. symbol parameter test condition min max unit c out output capacitance v out = 0v 5 pf c in input capacitance v in = 0v 5 pf -36 0.8v cc 0.2v cc 0.7v cc 0.3v cc
m93s66-125 M93S56-125 m93s46-125 dc and ac parameters doc id 022567 rev 1 21/28 table 8. dc characteristics (m93sx6-w, device grade 3) symbol parameter test condition min. max. unit i li input leakage current 0v v in v cc 2.5 a i lo output leakage current 0v v out v cc , q in hi-z 2.5 a i cc supply current (cmos inputs) v cc = 5 v, s = v ih , f = 2 mhz 2 ma v cc = 2.5 v, s = v ih , f = 2 mhz 1 ma i cc1 supply current (stand-by) v cc = 2.5 v, s = v ss , c = v ss 5 a v il input low voltage (d, c, s) ?0.45 0.2 v cc v v ih input high voltage (d, c, s) 0.7 v cc v cc + 1 v v ol output low voltage (q) v cc = 5 v, i ol = 2.1ma 0.4 v v cc = 2.5 v, i ol = 100a 0.2 v v oh output high voltage (q) v cc = 5 v, i oh = ?400a 2.4 v v cc = 2.5 v, i oh = ?100a v cc ?0.2 v
dc and ac parameters m93s66-125 M93S56-125 m93s46-125 22/28 doc id 022567 rev 1 table 9. ac characteristics (m93sx6-w, device grade 3) test conditions specified in table 5 and table 6 symbol alt. parameter min. max. unit f c f sk clock frequency d.c. 2 mhz t prvch t pres protect enable valid to clock high 50 ns t wvch t pes write enable valid to clock high 50 ns t clprx t preh clock low to protect enable transition 0 ns t slwx t peh chip select low to write enable tr a n s i t i o n 250 ns t slch chip select low to clock high 50 ns t shch t css chip select set-up time 50 ns t slsh (1) 1. chip select input (s ) must be brought low for a minimum of t slsh between consecutive instruction cycles. t cs chip select low to chip select high 200 ns t chcl (2) 2. t chcl + t clch 1 / f c . t skh clock high time 200 ns t clch (2) t skl clock low time 200 ns t dvch t dis data in set-up time 50 ns t chdx t dih data in hold time 50 ns t clsh t sks clock set-up time (relative to s) 50 ns t clsl t csh chip select hold time 0 ns t shqv t sv chip select to r eady/busy status 200 ns t slqz t df chip select low to output hi-z 100 ns t chql t pd0 delay to output low 200 ns t chqv t pd1 delay to output valid 200 ns t w t wp erase/write cycle time 5 ms
m93s66-125 M93S56-125 m93s46-125 dc and ac parameters doc id 022567 rev 1 23/28 figure 9. synchronous timing (start and opcode input) figure 10. synchronous timing (read) pre w c s d op code op code start start op code input tchdx tdvch tclsh tclch tchcl twvch tprvch ai02025 tshch ai002026 c d q address input hi-z tdvch tclsl a0 s data output tchqv tchdx tchql an tslsh tslqz q15 q0
dc and ac parameters m93s66-125 M93S56-125 m93s46-125 24/28 doc id 022567 rev 1 figure 11. synchronous timing (write) pre w c s d hi-z tw tdvch ai02027 q tclprx tslwx tclsl tchdx tslsh tslqz busy tshqv ready write cycle address/data input an a0/d0 tslch
m93s66-125 M93S56-125 m93s46-125 package mechanical data doc id 022567 rev 1 25/28 9 package mechanical data in order to meet environmental requirements, st offers the m93sx6-125 devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at www.st.com . figure 12. so8 narrow ? 8-lead plastic small outline, 150 mils body width, package outline 1. drawing is not to scale. table 10. so8 narrow ? 8 lead plastic small outline, 150 mils body width, mechanical data symbol mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. typ. min. max. typ. min. max. a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 4.80 5.00 0.189 0.197 e 3.80 4.00 0.150 0.157 e 1.27 ? ? 0.050 ? ? h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 0.90 0.016 0.035 a 08 08 n8 8 cp 0.10 0.004 so-a e n cp b e a d c l a1 1 h h x 45?
part numbering m93s66-125 M93S56-125 m93s46-125 26/28 doc id 022567 rev 1 10 part numbering devices are shipped from the factory with the memory content set at all 1s (ffh). for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 11. ordering information scheme example: m93s66 ? w mn 3 t p /s device type m93 = microwire serial access eeprom (x16) with block protection device function 66 = 4 kbit (256 x 16) 56 = 2 kbit (128 x 16) 46 = 1 kbit (64 x 16) operating voltage w = v cc = 2.5 to 5.5 v package mn = so8 (150 mil width) device grade 3 = automotive: device tested with high reliability certified flow over ?40 to 125c option blank = standard packing t = tape & reel packing plating technology blank = standard snpb plating p = lead-free and rohs compliant process /s = manufacturing technology code
m93s66-125 M93S56-125 m93s46-125 revision history doc id 022567 rev 1 27/28 11 revision history table 12. document revision history date revision changes 14-mar-2012 1 initial release.
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